The present invention relates generally to semiconductor devices, and more particularly, to nanowire-type field effect transistors (FETs).
FETs are widely used in the electronics industry for switching, amplification, filtering, and other tasks related to both analog and digital electrical signals. Most common among these are metal-oxide-semiconductor field-effect transistors (MOSFET), in which a gate structure is energized to create an electric field in an underlying channel region of a semiconductor body, by which electrons or holes are allowed to travel through the channel between a source region and a drain region of the semiconductor body. Complementary metal-oxide-semiconductor field-effect transistor, which are typically referred to as CMOS devices, have become widely used in the semiconductor industry. These CMOS devices include both n-type and p-type (NMOS and PMOS) transistors, and therefore promote the fabrication of logic and various other integrated circuitry.
The escalating demands for high density and performance associated with ultra large scale integrated (VLSI) circuit devices have required certain design features, such as shrinking gate lengths, high reliability and increased manufacturing throughput. The continued reduction of design features has challenged the limitations of conventional fabrication techniques. Gate-all-around semiconductor devices, such as nanowire-type FETs, typically include nanowires that are suspended above a substrate such that gate stacks may be formed around the channel region of the nanowire. Nanowire-type FETs may be fabricated as a stacked nanowire FET, which include a number of suspended nanowires stacked in a common plane above the substrate. The stacking of the suspended nanowires allows a number of FET devices to occupy a space on the substrate.